型号 封装 在线定购
S3C2440A40-YQ80(查看) 289FBGA


技术资料—— S3C2440 PDF技术资料

S3C2440 概述

S3C2440 is a derivative product of Samsung's S3C24XXX family of microprocessors for mobile communication market. The S3C2440 / S3C2440A / S3C2440A-40's main enhancement over the baseline product, S3C2410X, is the addition of camera interface for multimedia messaging services.

The S3C2440 features an ARM920T core, a 16/32-bit RISC microprocessor, to provide hand-held devices and general applications with cost-effective, low-power, and high performance micro-controller solution in a small form-factor. The S3C2440 / S3C2440A / S3C2440A-40 is developed using 0.13 um CMOS standard cell and a memory compiler. In addition, it adopts a new bus architecture called Advanced Microcontroller Bus Architecture (AMBA).

By providing a comprehensive set of common system peripherals, the S3C2440 / S3C2440A minimizes the overall system costs and eliminates the need to configure additional components. The S3C2440 / S3C2440A / S3C2440A-40 includes the following components: separate 16 KB instruction and 16 KB data cache, MMU to handle virtual memory management, TFT& STN LCD controller, NAND flash boot loader, system manager (chip select logic and SDRAM controller), 3-ch UART, 4-ch DMA, 4-ch timers with PWM, I/O ports, RTC, 8-ch 10-bit ADC and touch screen interface, camera interface, AC97 audiocodec interface, IIC-BUS interface, IIS-BUS interface, USB host, USB device, SD host & multimedia card interface, 2-ch SPI and PLL for clock generation.

S3C2440 特性

  • S3C2440A: the A Version of the S3C2440
  • S3C2440 / S3C2440A Operating Voltage Range:
    • Core: 1.20V for 300MHz (S3C2440A-30)
         1.30V for 400MHz (S3C2440A-40)
    • Memory: 1.8V/ 2.5V/3.0V/3.3V
    • I/O: 3.3V
  • Around 1.2V internal, 1.8V/2.5V/3.3V memory, 3.3V external I/O microprocessor with 16KB I-Cache/16KB DCache/
  • External memory controller (SDRAM Control and Chip Select logic)
  • LCD controller (up to 4K color STN and 256K color TFT) with LCD-dedicated DMA
  • 4-ch DMA controllers with external request pins
  • 3-ch UARTs (IrDA1.0, 64-Byte Tx FIFO, and 64-Byte Rx FIFO)
  • 2-ch SPls
  • IIC bus interface (multi-master support)
  • IIS Audio CODEC interface
  • AC’97 CODEC interface
  • SD Host interface version 1.0 & MMC Protocol version 2.11 compatible
  • 2-ch USB Host controller / 1-ch USB Device controller (ver 1.1)
  • 4-ch PWM timers / 1-ch Internal timer / Watch Dog Timer
  • 8-ch 10-bit ADC and Touch screen interface
  • RTC with calendar function
  • Camera interface (Max. 4096 x 4096 pixels input support. 2048 x 2048 pixel input support for scaling)
  • 130 General Purpose I/O ports / 24-ch external interrupt source
  • Power control: Normal, Slow, Idle and Sleep mode
  • On-chip clock generator with PLL