型号 封装 在线定购
P89LPC930FDH(查看) TSSOP28


技术资料—— P89LPC930 PDF技术资料

P89LPC930 概述


P89LPC930 参数
P89LPC930 存储器
FLASH (kB)   4
RAM (B)   256
EEPROM (B)   -
P89LPC930 其他参数
fmax (MHz)   18
UART   1
I²C   1
SPI   1
ADC   -
DAC   -
Timers   2
PWM   2
VDD (V)   2.4-3.6
P89LPC930 封装与引脚

P89LPC930 特性

  • high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is 6 times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI.
  • 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V).
  • 4 kB/8 kB Flash code memory with 1 kB sectors, and 64-byte page size.
  • Byte-erase allowing code memory to be used for data storage.
  • Flash program operation completes in 2 ms.
  • Flash erase operation completes in 2 ms.
  • 256-byte RAM data memory.
  • Two 16-bit counter/timers. Each timer may be configured to toggle a port output upon timer overflow or to become a PWM output.
  • Real-Time clock that can also be used as a system timer.
  • Two analog comparators with selectable inputs and reference source.
  • 400 kHz byte-wide I2C-bus communication port.
  • SPI communication port.