型号 封装 在线定购
H57V1262GTR-60C(查看) TSOPII54
H57V1262GTR-75C(查看) TSOPII54


技术资料—— H57V1262GTR PDF技术资料
H57V1262GTR 参数
H57V1262GTR 性能参数
容量 128Mb
结构 4Banks x 2Mbits x 16
工作电压 (V) 3.3
工作温度范围 0 to 70 °C (商业级)
–40 to 85 °C (工业级)
H57V1262GTR 封装与引脚

H57V1262GTR 概述

The H57V1262GTR series is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth.)
H57V1262GTR series is organized as 4banks of 2,097,152 x 16.
H57V1262GTR is offering fully synchronous operation referenced to a positive edge of the clock.
All inputs and outputsare synchronized with the rising edge of the clock input.
The data paths are internally pipelined to achieve very highbandwidth.
All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or writecycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-quential or interleave).

H57V1262GTR 特性

  • Voltage: VDD, VDDQ 3.3V supply voltage
  • All device pins are compatible with LVTTL interface
  • 54 Pin TSOPII (Lead Free Package)
  • All inputs and outputs referenced to positive edge of system clock
  • Data mask function by UDQM, LDQM
  • Internal four banks operation
  • Auto refresh and self refresh
  • 4096 Refresh cycles / 64ms
  • Programmable Burst Length and Burst Type
    • 1, 2, 4, 8 or full page for Sequential Burst
    • 1, 2, 4 or 8 for Interleave Burst
  • Programmable CAS Latency; 2, 3 Clocks
  • Burst Read Single Write operation
  • Operating Temperature
    • Commercial Temperature (0 to 70 °C)
    • Industrial Temperature (–40 to 85 °C)
  • This product is in compliance with the directive pertaining of RoHS