|结构||4Banks x 2Mbits x 16|
|工作温度范围||0 to 70 °C (商业级)
–40 to 85 °C (工业级)
The H57V1262GTR series is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth.)
H57V1262GTR series is organized as 4banks of 2,097,152 x 16.
H57V1262GTR is offering fully synchronous operation referenced to a positive edge of the clock.
All inputs and outputsare synchronized with the rising edge of the clock input.
The data paths are internally pipelined to achieve very highbandwidth.
All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or writecycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-quential or interleave).